In current memory systems, data stored in volatile memories (e.g., DRAM) must be periodically refreshed to compensate for inherent leakage of capacitors in memory cells. In essence, refreshing includes, for example, reading data out of each row of memory and subsequently writing the data back to the same respective row. As a result, the original charge level on each capacitor is restored and data preserved.
While many approaches for using memory refreshes to compensate for leakage are well known in the art, these approaches have struggled when applied to the increasingly demanding operating speeds and applications of memories today. For example, in some instances, a particular row or rows of memory may be repeatedly accessed. Data stored by rows physically adjacent the repeatedly accessed row of memory may be degraded due to leakage resulting from the repeated access.
Accessing a row in this manner may include switching between providing an activation voltage and a deactivation voltage to a word line associated with a row to activate and deactivate the row, respectively. The more negative the deactivation voltage, the greater the leakage incurred during repeated accesses. While some approaches attempt to address this problem by decreasing the voltage swing to reduce leakage, these approaches have resulted in increased leakage in other aspects, such as in access devices connected to the word line associated with the accessed row.